1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a memory cell array structure and method capable of improving bit line precharge time (tRP).
2. Description of the Related Art
In a semiconductor memory device, bit line precharge time is an important parameter that decides operational frequency characteristics. In a semiconductor memory device such as a DRAM, a precharge operation disables a word line and a bit line which are enabled by active operation. In other words, the precharge operation equalizes the voltage of the word line to 0V, and equalizes a bit line and a complementary bit line to a precharge voltage level.
The definition of precharge time (tRP) will be described with reference to FIG. 1. Referring to FIG. 1, a word line WL which is previously enabled is disabled in response to the activation of a precharge signal PRECH. Soon after, a bit line BL and a complementary bit line BLB are precharged from a particular voltage level previously sensed by a sense amplifier, that is, from a fully swung voltage level, to a precharge voltage VBL level.
In an active interval introduced by activation of a sensing signal BSENSE, the word line WL is enabled and the bit line BL and the complementary bit line BLB charge-share memory cell data. Thus, there is a difference in voltage between the bit line BL and the complementary bit line BLB.
The bit line BL and the complementary bit line BLB have a voltage level fully swung by operations of the sense amplifier. Here, the time required for the sensing signal BSENSE to be activated after the precharge signal PRECH is activated is called the precharge time tRP.
The precharge time tRP is required for ensuring that the sense amplifier senses the voltage levels of the bit line BL and the complementary bit line BLB. As the precharge time tRP becomes shorter, the operational speed of a DRAM becomes faster.
FIG. 2 is a diagram of a conventional memory cell array structure 200. Referring to FIG. 2, the memory cell array structure 200 is formed to make two adjacent memory cell blocks ((MB0, MB1), (MB1, MB2), . . . , or (MBN-1, MBN)) respectively share one sense amplifier unit 220 placed between them.
Each of the sense amplifier units 210 arranged at the edge of the memory cell array 200 includes a bit line sense amplifier 211, an isolation transistor unit 212, and an equalizing and precharging unit 213. The isolation transistor unit 212 connects the memory cell block MB0 to the bit line sense amplifier 211.
Each of the sense amplifier units 220 arranged within the memory cell array 200 includes a bit line sense amplifier 221, two isolation transistor units 222 and 223, and two equalizing and precharging units 224 and 225. The two isolation transistor units 222 and 223 connect one of the memory cell blocks MB1 and MB2 to the bit line sense amplifier 221. Particularly, the isolation transistor 222 connects the memory cell block MB1 to the bit line sense amplifier 221 in response to a first isolation signal Piso_1.
In the case of sensing the data of the memory cell block MB1, the isolation transistor unit 223 is turned off in response to a second isolation signal Piso_2, and thus, the memory cell block MB2 is not connected to the bit line sense amplifier 221. At the same time, the equalizing and precharging unit 225 precharges bit lines BL and BLB of the memory cell block MB2 to a precharge voltage level.
If selection of the memory cell block MB1 is canceled, in other words, if operation of the bit line sense amplifier 221 for sensing and amplifying the data of memory cells MC0 and MC1 is stopped, the bit line BL and its complementary bit line /BL of the memory cell block MB1 are precharged to a voltage level VBL by the equalizing and precharging unit 224.
At the same time, as mentioned above, the bit line BL and complementary bit line /BL of the memory cell block MB2 have been precharged by the equalizing and precharging unit 225. If the isolation transistor units 222 and 223 are turned on in response to the first and second isolation signals Piso_1 and Piso_2, the bit line BL and complementary bit line /BL of the memory cell block MB1 are connected to the bit line BL and complementary bit line /BL of the memory cell block MB2, respectively.
The speed of precharging the bit line BL and complementary bit line /BL of the memory cell block MB1 is determined by the bit line BL and complementary bit line /BL of the memory cell block MB2, as well as the equalizing and precharging unit 224. However, the memory cell blocks MB0 and MBN placed at the edge of the memory cell array 200 do not have any counterpart placed at the opposite side and sharing the bit line sense amplifier 211, and thus, the speed of precharging the bit line BL and complementary bit line /BL of each of the memory cell blocks MB0 and MBN is determined by only the equalizing and precharging unit 213.
The speed of precharging the bit line BL and complementary bit line /BL of each of the memory cell blocks MB0 and MBN is thus lower than the speed of precharging the bit line BL and complementary bit line /BL of each of the memory cell blocks MB1 through MBN-1. Therefore, as more memory cells are allotted to each of the memory cell blocks MB0 through MBN, the speed of precharging the bit line BL and the complementary bit line /BL is reduced more considerably. This is because the load on the length of the bit line BL and complementary bit line /BL connected to the memory cells, that is, the amount of electric charge stored in a line capacitor, is not a negligible amount.
Accordingly, the bit line precharge time tRP of the memory cell blocks MB1 through MBN-1 placed at the inner part of the memory cell array 200 is different from that of the memory cell blocks MB0 and MBN located at the edge of the memory cell array 200. Thus, the operational speed of a DRAM is restricted by the precharge time tRP of the memory cell blocks MB0 and MBN, so that the DRAM cannot operate at a high speed. Therefore, a memory cell array structure capable of reducing the precharge time tRP of the memory cell blocks MB0 and MBN placed at its edge is required.
The present invention is therefore directed to a semiconductor memory device which substantially overcomes one or more of the problems due to the limitations and disadvantages of the related art.
To solve the above problems, it is a first object of the present invention to provide a memory cell array structure which is capable of reducing precharge time.
It is a second object of the present invention to provide a method of precharging a bit line which is capable of reducing precharge time.
Accordingly, to achieve the first and other objects, there is provided a semiconductor memory device having a memory cell array structure which includes memory cell blocks in each of which a plurality of memory cells are arranged; a first sense amplifier unit arranged between two adjacent memory cell blocks among the memory cell blocks and shared by the two adjacent memory cell blocks, that senses and amplifies the data of the memory cells; a second sense amplifier unit connected to a memory cell block at an edge of the memory cell array structure, which senses and amplifies the data of the memory cells; and a dummy capacitor region including a plurality of capacitors connected between a dummy bit line and a complementary dummy bit line, which are connected to a bit line and a complementary bit line of the memory cell block at the edge of the memory cell array structure.
The capacitors may have a capacitance equal to the line capacitance of the bit line. The capacitors may consist of cell capacitors of the memory cells.
A dummy capacitor region according to a further embodiment of the present invention includes a plurality of capacitors connected between a power supply and either a dummy bit line or a complementary dummy bit line, which is connected to a bit line or a complementary bit line of the memory cell block at the edge of the memory cell array structure.
A dummy capacitor region according to a still further embodiment of the present invention includes a plurality of capacitors connected between a dummy bit line and a complementary dummy bit line, one end of the plurality of capacitors being connected to a bit line and a complementary bit line of the memory cell block at the edge of the memory cell array structure, and the other end of the plurality of capacitor being connected to a power supply.
To achieve the second and other objects, there is provided a method of precharging a bit line in a semiconductor memory device having a common sense amplifier structure, including precharging a plurality of capacitors connected between a dummy bit line and a complementary dummy bit line in a dummy capacitor region; disconnecting the dummy bit line and the complementary dummy bit line from a bit line sense amplifier; connecting a bit line and a complementary bit line of a memory cell block to the bit line sense amplifier and sensing memory cell data; stopping operation of the bit line sense amplifier and precharging the bit line and the complementary bit line; and connecting the bit line and the complementary bit line to the dummy bit line and the complementary dummy bit line, respectively.
According to the semiconductor memory device having the memory cell array structure of the present invention, the speed of precharging the bit line and complementary bit line of a memory cell block arranged at an edge of the memory cell array structure is almost the same as the speed of precharging the bit line and complementary bit line of a memory cell block arranged at an inner part of the memory cell array structure.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.